The invention relates to a circuit arrangement for retrieving data contained in binary data signals wherein a phase control circuit generates reference signals allocated to the data signals in terms of phase and frequency. An integration stage is provided and a decoder stage retrieves the data contained in the data signals by use of the reference signals.
A circuit arrangement for retrieving data contained in binary data signals is known from German OS No. 22 21 134, incorporated herein by reference, wherein the binary data signals are multiplied by reference signals generated in a phase control circuit. The product of the two signals is subsequently integrated and the operation sign of the integration is interrogated in a decoder stage at prescribed points in time in order to retrieve the data contained in the binary data signals.
The known circuit arrangement permits a largely trouble-free recognition of the data contained in the data signals insofar as the reference signals exhibit no phase deviation relative to the nominal progressions of the data signals. Since the phase control circuit however is driven by the potentially disrupted data signals, the phase relation between the reference signals output by the phase control circuit and the data signals is, for example, constantly disturbed due to additional signal edges. The disturbing influence mainly depends on the spacing between the noise and nominal edges of the data signals.